P u b l i c a t i o n s

J. López, P. Reviriego, J.A. Maestro, M. Sánchez-Renedo, V. Petrovic, J. F. Dufour and J.S. Weil, “SEPHY: An Ethernet Physical Layer Transceiver for Space”, presented at AMICSA 2016.

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A. Breitenreiter, J. López, P. Reviriego, D. González and M. Krstic, “Eine Methode zur Verifikation von Mixed-Signal-ASIC”. In Proceedings of the GI Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2017)", 73, 2017.

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P. Reviriego, J. Lopez, M. Sanchez-Renedo, V. Petrovic, J. F. Dufour and J. S. Weil, "The space Ethernet physical layer transceiver (Sephy) project: a step towards reliable Ethernet in space," in IEEE Aerospace and Electronic Systems Magazine, vol. 32, no. 1, pp. 24-28, 2017.

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A. Breitenreiter and M. Krstić, “An Automated Design and Verification Flow for Fault-Tolerant ASICs”. An Abstract at  Biannual European - Latin American Summer School on Design, Test and Reliability. Rotterdam, The Netherlands, 2017.

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Y. Li, A. Breitenreiter, M. Andjelkovic, O. Schrape and M. Krstić, "Flip-Flop SEUs Mitigation Through Partial Hardening of Internal Latch and Adjustment of Clock Duty Cycle", the 21st IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2018.

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C. M. Navaneetha, A. Breitenreiter, M. Ulbricht, M. Krstić, “A Methodology to Verify Digital IP’s Within Mixed-Signal Systems”, the 21st IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2018.

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